[最も好ましい] Verilog Ifdef Or Condition 643764-Verilog Ifdef Conditional
Web33 Data types¶ Data types can be divided into two groups as follows, Net group Net group represents the physical connection between components eg wire, wand and wor etcIn the tutorials, we will use only one net data type ie ‘wire’,WebVerilog `ifdef Conditional Compilation // Style #1 Only single `ifdef `ifdef // Statements `endif // Style #2 `ifdef with `else part `ifdef // Statements `else //Web or #if defined (LINUX) defined (ANDROID) // your code here #endif /* LINUX ANDROID */ Both above are the same, which one you use simply depends on your taste Verilog Basic Language Constructs Lexical Convention Data Types And So On Spring Ppt Download Verilog ifdef conditional